Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are design generation, synthesis, placement, and routing of the system on the target device.
The use of pre-designed blocks of logic, known as intellectual property (IP) cores, have increased with current systems. Some systems utilize dozens to hundreds of IP cores. The IP cores may be used for implementing processors, memory controllers, or components that perform other functionalities. Each IP core may present a unique set of interfacing signals with its own requirements. In order to instantiate an IP core into a system, appropriate adaptation logic between components needs to be selected when designing an interconnect architecture for the system.
When designing an interconnect architecture for a system, some design tools apply pre-defined strategies for the system. Other design tools apply hard constraints which limit it from fully exploring available design options.